Computer processing systems use several kinds of memory structures. Specialized write circuitry may be used for writing data to be stored in the bit cells of the memory arrays. For example, dual voltage memory array designs include memory cells which may be placed in a high voltage domain to improve data retention, while peripheral logic such as write drivers may be placed in a low voltage domain to reduce their power consumption. Therefore, voltage level shifters may be employed to shift signals from the write drivers from the low voltage domain to the high voltage domain.
In the case of memory structures organized into multiple memory banks, conventional designs use a global write bitline driver to generate a global write bitline signal for use across multiple memory banks in the low voltage domain. The global write bitline signal is voltage level shifted, with dedicated voltage level shifters at input/output ports of each of the multiple memory banks, to convert the global write bitline signal into the high voltage domain at each memory bank. The global write bitline signal is then gated at each memory bank, for example, with a write enable signal for the memory bank, to generate the local write bitline signal for the memory bank. Such designs with multiple dedicated voltage level shifters for the multiple memory banks are expensive in terms of area and also increase both dynamic and static power consumption.
On the other hand, designing large global write bitline drivers to be placed in the high voltage domain along with the memory banks is also not a practical solution to reduce costs associated with the dedicated voltage level shifters, because such high voltage domain global write bitline drivers consume significant power and may offset any benefits that may be realized by avoiding the dedicated voltage level shifters.
Accordingly, there is a recognized need in the art for efficient and low power designs for generating local write bitline signals in the high voltage domain for the various memory banks of a memory system, while avoiding the aforementioned drawbacks of conventional designs.